Etched

DFT Intern

Listed by employer · Checked

Older posting · still listed ·

  • onsite
  • Intern
  • ASIC
  • San Jose
Work arrangement
onsite
Employment
Intern
Stated compensation
Not specified
Apply on company website ↗
01 / A QUICK CHECK BEFORE YOU APPLY

Does the location policy fit?

Choose where you would work from. We’ll compare it with the posting’s stated requirements.

Choose the country you will work from. You can change this anytime.

Country and sponsorship changes take effect when you click Check eligibility.

Choose a country to check geographic compatibility. The source requirements are available below.

Source: ashbyChecked Original posting ↗
This is an older posting.

The employer’s posting date is more than 60 days ago. It remained listed at our last successful check; it may be a long-running or evergreen opening. Confirm availability on the original posting before applying.

Browse jobs posted in the past 60 days →

Requirements

1 with evidence8 unclear or unstated
Remote policy
onsite
“Provider workplace type: onsite”
From employer posting metadata
Employment type
Intern
9 fields not stated in this posting
Employer sponsorship
Not specified
Geographic scope
Not specified
Degree requirement
Not specified
Security clearance
Not mentioned
Timezone / hours
Not specified
Citizenship requirement
Not mentioned
Minimum experience (years)
Not specified
Work authorization
Not specified
Compensation
Not specified

These details were not stated in the tracked posting. Confirm with the employer.

READ IT IN THE EMPLOYER’S OWN WORDS

Original job description

Reading view uses normalized posting text so exact evidence excerpts can be highlighted.

About Etched Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary
Read full descriptionShow less description
As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Spring '27, and Summer '27 interns. You may be a good fit if you have Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field. Familiarity with a hardware description language (Verilog or SystemVerilog) Exposure to ASIC or SoC design concepts Familiarity with digital logic design fundamentals Familiarity with standard ASIC design flow steps (synthesis, STA, DFT) Familiarity with scripting in Python, Tcl, or another language Are able to learn quickly about transformers and other aspects of modern artificial intelligence Strong candidates may also have experience with Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression Experience with Tessent or similar DFT tooling Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF) Exposure to DFT flow automation or regression infrastructure Familiarity with clocking and reset schemes We encourage you to apply even if you do not believe you meet every single qualification. Program details 12-week paid internship Generous housing support for those relocating Daily lunch and dinner in our office Based at our office in San Jose, CA Direct mentorship from industry leaders and world-class engineers Opportunity to work on one of the most important problems of our time For any questions, contact internships@etched.com. How we’re different Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.  We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
Original formatting and links

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As a DFT Intern at Etched, you will help review and refine DFT flow automation to support chip-level regression on Caelius. You will work across frontend and backend design teams, contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations), and develop flows for various ATPG fault models. You do not necessarily need prior DFT experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. We are looking for Spring '27, and Summer '27 interns.

You may be a good fit if you have

  • Progress towards a Bachelor's, Master's, or PhD degree in electrical engineering, computer engineering, or a related field.

  • Familiarity with a hardware description language (Verilog or SystemVerilog)

  • Exposure to ASIC or SoC design concepts

  • Familiarity with digital logic design fundamentals

  • Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)

  • Familiarity with scripting in Python, Tcl, or another language

  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Strong candidates may also have experience with

  • Knowledge of DFT concepts such as MBIST, scan insertion, and scan compression

  • Experience with Tessent or similar DFT tooling

  • Familiarity with ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)

  • Exposure to DFT flow automation or regression infrastructure

  • Familiarity with clocking and reset schemes

We encourage you to apply even if you do not believe you meet every single qualification.

Program details

  • 12-week paid internship

  • Generous housing support for those relocating

  • Daily lunch and dinner in our office

  • Based at our office in San Jose, CA

  • Direct mentorship from industry leaders and world-class engineers

  • Opportunity to work on one of the most important problems of our time

For any questions, contact internships@etched.com.

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

 

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

Similar roles

All Etched jobs →

No similar roles found yet — browse all Etched jobs.

THE JOB ELIGIBILITY CHECKER

Check a job